Sanyo VPC SX 560 Digital Camera user manual

1. IC Configuration

1-1. CA1 CIRCUIT DESCRIPTION

Around CCD block

2. IC903 (CCD)

[Structure]

Interline type CCD image sensor

Optical size

Diagonal 8 mm (1/2 type)

Effective pixels

1392 (H) 1040 (V)

Pixels in total

1434 (H) 1050 (V)

Actual pixels

1360 (H) 1024 (V)

Optical black

Horizontal (H) direction: Front 2 pixels, Rear 40 pixels

Vertical (V) direction:

Front 8 pixels, Rear 2 pixels

Dummy bit number

Horizontal : 20 Vertical : 3

Horizontal register

Photo sensor

Fig. 1-2. CCD Block Diagram

Pin Description

Vertical register transfer clock

-8.0 V, 0 V

V ? 2A, V ? 2B Vertical register transfer clock

-8.0 V, 0 V, 15 V

Vertical register transfer clock

-8.0 V, 0 V

Signal output

Circuit power

Substrate clock

Different from every CCD

Substrate bias

Reset gate clock

12 V, 17 V

Horizontal register transfer clock

Horizontal register transfer clock

Aprox. 7 V

Different from every CCD

Protection transistor bias

Table 1-1. CCD Pin Description

When sensor read-out

3. IC902, IC904, IC908 (H Driver) and IC907 (V Driver)

4. IC905 (CDS, AGC Circuit and A/D Converter)

An H driver and V driver are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD.

IC902, IC904 and IC908 are inverter IC which drives the horizontal CCDs (H1 and H2). In addition the XV1-XV3 signals which are output from IC102 are the vertical transfer clocks, and the XSG1 and XSG signal which is output from IC102 is superimposed onto XV2A and XV2B at IC907 in order to generate a ternary pulse. In addition, the XSUB signal which is output from IC102 is used as the sweep pulse for the electronic shutter, and the RG signal which is output from IC102 is the reset gate clock.

The video signal which is output from the CCD is input to Pin

(30) of IC905. There are S/H blocks inside IC905 generated from the XSHP and XSHD pulses, and it is here that CDS

(correlated double sampling) is carried out.

After passing through the CDS circuit, the signal passes through the AGC amplifier. It is A/C converted internally into a 10-bit signal, and is then input to IC102 of the CA2 circuit board. The gain of the AGC amplifier is controlled by serial data which is output from IC102 of the CA2 circuit board.